Faculty of Engineering, Computing and Science (FECS) EEE 40002 Integrated Circuit Design.
Swinburne University of Technology
Faculty of Engineering, Computing and Science (FECS) EEE 40002 Integrated Circuit Design
Design of Dynamic RAM Controller
1. This laboratory is worth 1/3 of 40% of your total Final marks
2. READ the lab through carefully and make sure you understand what you are required to do.
3. Submit your report (written using IEEE format) as a INDIVIDUAL.
You have to hand in a lab report written using IEEE format (refer to attached paper for guidelines) that contains the following:
1. Discuss the design interface strategies and the internal structure of the DRAMs. (You need to research this and summarize the technical information and compare this design to other strategies).
2. Synthesis results and the estimated speed of the circuit.
3. Indicate the speed at which the circuit operates. Compare your results to other group results
4. Source code and test bench files along with waveforms & comments added to verify the functionality of design.
The lab report is an important part of the laboratory. Write it carefully, be clear and well organized. Kindly refer to the marking rubric for the grading criteria.
Design a simplified and shared dynamic RAM controller circuit which has the following specifications:
The inputs to the circuit are a 10 bit address (ADDRIN), a read signal (RD), a write signal (WR), and an enable signal (ALE). This circuit does not function until ALE becomes 1, then the 10-bit ADDRIN is loaded in as a row address (7 downto 4) and a column address (3 downto 0) bit registers. Also Read and Write, address line 8 (B0) and 9 (B1) signals are “stored”. Subsequently, the row address is outputted at ADDROUT along with the row address strobe (RAS) signal (active low) which is generated one clock cycle later. The RAS (active low) signal is outputted according to rules in table 1. Then, the column address is outputted at ADDROUT along with the column address strobe (CAS) signal (active low), which is generated one clock cycle later. Finally, if the operation is a write operation (RD = 0, WR = 1), then the WE output is 1.Otherwise for a read operation (RD = 1, WR = 0), the WE output remains 0. The controller returns to the initial state after generating all the required signals.
You are also required to implement the 4 memory banks as well. A memory bank remains in the idle state until it receives a negative RAS signal (active low) from the controller. When it occurs, the selected memory bank stores the address from ADDROUT as row address. The same memory bank then waits for a negative CAS signal (active low) from the controller. When it occurs, it stores the address from ADDROUT as column address. At the same time, the memory bank also checks WE for the operation to perform. If a write operation is instructed, the bank stores the value of DATAIN at the specified address. Else if a read operation is instructed, data at the specified address is produced at DATAOUT. The minimum length for the data is 2-bit. Once the operation is completed, the bank returns to idle.
Design the DRAM controller and memory bank as separate vhd files. Then, produce a top level entity file to connect the designs. Note that you do not have to write the code for the memory bank 4 times to produce 4 memory banks in your design. Since all the banks are identical, you only need to code them once and instantiate the design 4 times in the top level.
Next design a testbench state machine which will provide test codes to your design. You may use the 7-segment LED and other LEDs to show the test sequence. Simulate and Synthesis your design, and analyse and discuss the simulated and synthesised outcome of your design Tips: you can reuse the clock divider codes from Miniproject 1 to slow down your clock.
Figure 1 Block connection of RAM Module
Figure 2 Sample Testbench block connections